The expense, propagation time delay, reduced data transmission rate and board real estate required to use conventional voltage level translators (e.g. Texas Instruments level translating buffer SN74LVT16244) are a problem in conventional circuit designs. Conventional approaches often use a series resistor with protection diode or resistive voltage divider. Both approaches suffer from RC time delay due to the resistive element coupled with the parasitic capacitance of the receiver input. For example, see slides 69-75 of the Xilinx App note at http://www.xilinx.com/products/spartan3e/sp3e_power.pdf.
Another level translation approach is to use series FET (Field Effect Transistor) devices such as Texas Instruments SN74CBT1G384 which provides a low impedance path for low voltage inputs but increases the series impedance to a high value once the low side output voltage exceeds a defined threshold. This approach carries the drawback of some minimal propagation delay and also requires the FET transistor plus an external voltage bias circuit.
A very similar approach is to use another form of series FET circuit such as implemented in the Texas Instruments SN74TVC3306 device. This approach carries the same disadvantages as described above for the SN74CBT1G384. Yet another approach is to use overvoltage-tolerant devices on the low voltage side inputs. This requires eliminating the low voltage input protection clamp diode to its supply voltage and thus is not amenable to all designs.
An object of the present invention is to overcome or ameliorate the problems described above. More specifically, an object of the present invention is to provide a minimal delay voltage level translator for use in integrated circuit logic devices.